Semiconductor wafer processing complexity has been increasing as the device size has been shrinking. A typical process has multiple different steps, with some advanced processes, such as plasma etching, may have twenty or even more steps. Each step has a multitude of knobs associated to optimize performance. Therefore, the space available to tune and optimize a given process is theoretically extremely large.
Process engineers use their experience and expertise to select a preliminary baseline process and fine tune the process based on a limited number of wafers (or portions of wafers, referred to as coupons) dedicated for design of experiment (DoE). The goal of DoE is to tailor the process to achieve desired specification on a wafer. However, dedicating full wafers or portions of wafers for DoE data collection consume valuable resources. Therefore, often the adopted process may be a viable one, but not necessarily the optimum solution.
Another bottleneck is introduced by insufficient in-line precision metrology data. For precision metrology, usually destructive techniques, such as transmission electron microscopy (TEM), are used. However, since TEM is very time consuming, it usually does not generate enough statistical data and adequate coverage across the wafer. Also, TEM cannot be integrated into the production line because it is a destructive technique.